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• OVERVIEW OF SWITCHING SUBSYSTEM MODELS FOR DIGITAL PHOTONIC COMPUTING DEVICES

  D.А. Sorokin, А.V. Kasarkin

  2024-11-10

  Abstract ▼

  This article examines options for organizing the switching subsystem of digital photonic computing
  devices, whose main task is to enable efficient computations in various problem domains. According to the
  authors, digital photonic computers should process information within a structural computing paradigm.
  This paradigm fundamentally differs from the classical von Neumann paradigm, as data transfer between
  functional elements is inseparable from processing. Therefore, developing a switching subsystem in digital
  photonic computing devices is a critical challenge. This subsystem must handle data dependencies between
  operations not only in time but also in space. Only under these conditions can data processing in
  photonic computing systems achieve performance that exceeds the performance of the most advanced
  electronic computing systems by two or more decimal orders. The article addresses issues of streaming
  data exchange between functional devices in a digital photonic computer. The authors developed and analyzed
  switching device models and methods for organizing the switching subsystem for sequential data
  processing, using a basis of photonic logic. The research established that structural organization of computations
  in digital photonic computers is feasible when data exchange is achieved through spatial switching
  of input and output channels of functional devices. In implementing digital photonic computers as
  universal devices aimed at a wide range of tasks, hierarchical and hierarchical-ring variants of the
  switching subsystem organization are most suitable for forming computational structures. However, these
  variants are characterized by high overhead for constructing switches. Therefore, in problem-oriented
  photonic computers designed for solving highly interconnected tasks with high specific performance, the
  use of orthogonal or toroidal switching subsystems is preferred. In this case, direct spatial switching between
  functional devices within a group, as well as between groups, should be ensured. These variants
  have higher requirements for the quality of physical channels formed between switches and functional
  devices, as well as between the switches themselves.

• THE ARCHITECTURE OF FUNCTIONAL DEVICES OF THE DIGITAL PHOTONIC COMPUTER

  I.I. Levin, D.А. Sorokin, А.V. Kasarkin

  2024-01-05

  Abstract ▼

  The paper covers the problems of the development of digital photonic computers. Along with
  quantum computers, they are one of the possible ways to overcome the crisis of computing performance.
  The data processing implementation in digital photonic computers at terahertz frequencies
  potentially provides the performance exceeding by two or more decimal orders of magnitude the
  performance of the most modern computing systems. Modern research suggests the prospects for
  the development of digital photonics. It can provide the performance, significantly exceeding the
  performance of microelectronic computers with the same calculation accuracy. At the same time,
  largely, the efforts of researchers are aimed at creating digital photonic logic elements, while
  architectural issues are considered very superficially. The authors consider the development problems
  of the digital photonic computer architecture, which could provide a solution to a wide class
  of computationally time-consuming problems in the paradigm of structural calculations.
  It is shown that the synchronization and switching subsystem must have a hierarchical topology
  with the configuration of information links both in the programming process of a photonic computer
  and in the process of solving problems to use this calculation paradigm. The principles of
  ensuring the performance and accuracy at solving problems on digital photonic computer with the
  chosen data representation method are considered. The authors have developed models of
  functional devices of basic arithmetic operations in the basis of photonic logic: the addition
  and multiplication in the IEEE 754 standard. The devices are implemented according to the
  scheme of linear conveyor with low-order processing forward. Unlike traditional microelectronics,
  the proposed approach to the construction of conveyor functional devices does not
  involve the use of latch registers. Its implementation leads to excessive hardware co sts in
  digital photonic logic. In addition, the branching factor of hardware information links b etween
  logical elements is limited at development the computational circuits. This will reducethe problem of signal attenuation. The FPGA has been used to prototype the developed functional
  addition and multiplication devices and to evaluate the performance of computing
  structures, implemented on DPC, similar to structures in mathematical physics problems at
  performing operations such as "matrix multiplication by vector".

• PERSPECTIVE ARCHITECTURE OF DIGITAL PHOTONIC COMPUTER

  I.I. Levin, D. А. Sorokin, А. V. Kasarkin

  2023-02-27

  Abstract ▼

  Modern computationally intensive tasks of mathematical physics require continuous increasing
  of the performance of computer equipment used for their highly efficient solution. However,
  at present, the development of their electronic components is slowing down due to limitations
  of technological production and operational processes. One of the ways to overcome the computer
  productivity growth crisis is the development of digital photonic computers (DPC). In the paper
  we suggest a promising DPC architecture, which consists of a functional subsystem, data stream
  synchronization and switching subsystems, and photonic-electronic interfaces of data exchange
  with external devices. We describe the principles of each subsystem. The functional subsystem is a
  set of DPC devices that provide 64-bit floating point arithmetic logic operations (according to the
  IEEE754 standard), implemented as linear pipelines with processing of least significant bits forward.
  The synchronization subsystem provides a single rate of data flow among various functional
  devices of the DPC, combined into a computing structure. According to the topology of the computing
  structure, the switching subsystem controls the data streams at the stage of DPC programming
  or during processing according to conditional transitions. For data exchange between the
  DPC and external devices, we suggest the technology of serialization of low-frequency parallel
  channels and deserialization of high-frequency serial channels. We give a theoretical evaluation of the performance of the computing structures implemented on the DPC, which is similar to the
  structures of mathematical physics problems concerning processing of special matrices. We show
  that DPCs, due to their clock frequency, can provide the performance that exceeds the performance
  of microelectronic devices by two and more orders of magnitude.

• A METHOD FOR SOLVING GRAPH NP-COMPLETE TASKS ON RECONFIGURABLE COMPUTER SYSTEMS BASED ON THE ITERATION PARALLELIZING PRINCIPLE

  A.V. Kasarkin

  2021-02-25

  Abstract ▼

  When we solve graph NP-complete tasks on multiprocessor systems, the growth of hardware
  resource does not lead to the proportional increase of the system performance, and hence, the task
  solution time is not always reasonable. The aim of our research, given in the paper, is minimization
  of the solution time of the task of maximal clique enumeration on reconfigurable computer
  systems (RCS). When we solve tasks on RCSs with the help of the method of parallelizing by layers,
  the growth of performance also slows down in spite of better scalability in comparison with
  multiprocessor implementations. In the paper, we suggest a method of parallel-pipeline application
  development for reconfigurable computer systems. The method is based on parallelizing bylayers for graph NP-complete tasks. We show that the bit representation of sets, which is used for
  the method of parallelizing by layers, is not efficient for the method of parallelizing by iterations.
  The new method has another organization of calculations; it processes unordered sets, whose
  elements are accessed not by addresses (as in arrays), but by values (names of vertices and names
  of edges of the graph). We show that the new method, based on parallelizing by iterations, provides
  ramping of the RCS real performance at much larger computational resource in comparison
  with the method of parallelizing by layers. Its specific performance is lower, because computing
  substructures are to process more intermediate data due to symbolic representation of sets.