THE ARCHITECTURE OF FUNCTIONAL DEVICES OF THE DIGITAL PHOTONIC COMPUTER

Abstract

The paper covers the problems of the development of digital photonic computers. Along with
quantum computers, they are one of the possible ways to overcome the crisis of computing performance.
The data processing implementation in digital photonic computers at terahertz frequencies
potentially provides the performance exceeding by two or more decimal orders of magnitude the
performance of the most modern computing systems. Modern research suggests the prospects for
the development of digital photonics. It can provide the performance, significantly exceeding the
performance of microelectronic computers with the same calculation accuracy. At the same time,
largely, the efforts of researchers are aimed at creating digital photonic logic elements, while
architectural issues are considered very superficially. The authors consider the development problems
of the digital photonic computer architecture, which could provide a solution to a wide class
of computationally time-consuming problems in the paradigm of structural calculations.
It is shown that the synchronization and switching subsystem must have a hierarchical topology
with the configuration of information links both in the programming process of a photonic computer
and in the process of solving problems to use this calculation paradigm. The principles of
ensuring the performance and accuracy at solving problems on digital photonic computer with the
chosen data representation method are considered. The authors have developed models of
functional devices of basic arithmetic operations in the basis of photonic logic: the addition
and multiplication in the IEEE 754 standard. The devices are implemented according to the
scheme of linear conveyor with low-order processing forward. Unlike traditional microelectronics,
the proposed approach to the construction of conveyor functional devices does not
involve the use of latch registers. Its implementation leads to excessive hardware co sts in
digital photonic logic. In addition, the branching factor of hardware information links b etween
logical elements is limited at development the computational circuits. This will reducethe problem of signal attenuation. The FPGA has been used to prototype the developed functional
addition and multiplication devices and to evaluate the performance of computing
structures, implemented on DPC, similar to structures in mathematical physics problems at
performing operations such as "matrix multiplication by vector".