PERSPECTIVE ARCHITECTURE OF DIGITAL PHOTONIC COMPUTER

Abstract

Modern computationally intensive tasks of mathematical physics require continuous increasing
of the performance of computer equipment used for their highly efficient solution. However,
at present, the development of their electronic components is slowing down due to limitations
of technological production and operational processes. One of the ways to overcome the computer
productivity growth crisis is the development of digital photonic computers (DPC). In the paper
we suggest a promising DPC architecture, which consists of a functional subsystem, data stream
synchronization and switching subsystems, and photonic-electronic interfaces of data exchange
with external devices. We describe the principles of each subsystem. The functional subsystem is a
set of DPC devices that provide 64-bit floating point arithmetic logic operations (according to the
IEEE754 standard), implemented as linear pipelines with processing of least significant bits forward.
The synchronization subsystem provides a single rate of data flow among various functional
devices of the DPC, combined into a computing structure. According to the topology of the computing
structure, the switching subsystem controls the data streams at the stage of DPC programming
or during processing according to conditional transitions. For data exchange between the
DPC and external devices, we suggest the technology of serialization of low-frequency parallel
channels and deserialization of high-frequency serial channels. We give a theoretical evaluation of the performance of the computing structures implemented on the DPC, which is similar to the
structures of mathematical physics problems concerning processing of special matrices. We show
that DPCs, due to their clock frequency, can provide the performance that exceeds the performance
of microelectronic devices by two and more orders of magnitude.