COMPARATIVE ANALYSIS OF TWO- AND SINGLE-STAGE BJT-JFET OPERATIONAL AMPLIFIERS
Abstract
Operational amplifiers with different number of amplifying stages realized on complementary
bipolar transistors and input field-effect transistors, with control p-n junction are considered.
For the elements of the master slice array MH2XA031 the original electrical schematics of three
amplifier variants (OAmp11.3, OAmp12, OAmp14) containing the same static mode bias block
and output stage are given. The OApm11.3 circuit contains an input differential stage in the form
of a " folded" cascode on p-JFETs and an intermediate amplifier stage on bipolar transistors. The
operational amplifier OAmp12 includes an input dual source-repeater on p-JFETs and an " folded"
cascode on complementary bipolar transistors. The OAmp14 circuit is realized on the basis of
dual source repeaters on p-JFETs and a high-precision voltage-to-current converter on complementary
bipolar transistors in the intermediate stages. The presented electrical circuits are characterized
by low zero offset voltage, relatively high voltage gain and can be used for application in special and dual-purpose equipment. When designing the Op-Amp circuits on the master slice array
MH2XA031 the search for a compromise combination of input current, noise level and voltage gain
was carried out, and special attention was paid to the choice of the operating mode of the input
JFETs. Single amplifier stage circuits, which typically provide lower noise, simple frequency correction,
and larger bandwidth, were investigated. For an adequate comparison of the developed amplifiers
the modeling of their static and dynamic parameters at the same operating mode of identical
circuit elements has been performed, which allowed to formulate recommendations on circuit synthesis
of operational amplifiers depending on the required combination of parameters. When optimizing
the operating mode of the transistors of the " folded" cascode with input JFETs, the recommendations
consisting in the necessity to increase the steepness of the input JFET transistors and the voltage
drop across the emitter resistors of the reference current sources were used.
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