IMPLEMENTATION OF RELATIONAL DEVICES OF DIGITAL SIGNALS MONITORING AND POLLING IN THE FPGA BASIS
Abstract
The requirements for modern means of technical control and functional diagnostics of
equipment for critical applications are formulated, one of which is the processing of diagnostic
information at a real-time pace. It is noted that for working with digital diagnostic signals, relational monitoring polling devices based on the apparatus of ordinal logic, which gives a significant
time gain over traditional binary logic, are promising. The hardware implementation of ordinal-
logical polling devices in the FPGA basis, along with the obvious advantages of the development
stage, will allow for operational reconfiguration of the internal structure to adapt to the
changing operating conditions of the control object. The hardware implementation of two known
devices is considered. A variable priority device is used to identify the sensor that has detected a
failure or malfunction, with the possibility of setting the sensor number from which the survey will
begin, and the direction of traversing the sensor tuple. The device of centralized control of a group
of objects is used to search for an extreme (maximum or minimum) digital diagnostic signal with
simultaneous determination of the number of the corresponding sensor in one clock cycle of the
monitoring and diagnostic system. The development of combinational data schemes of monitoring
survey devices was carried out by means of ISE Design Suite 14.7. The positive results of testing
the algorithms of the created models are presented, summarized in tables of the states of the inputs
and outputs of the circuits and illustrated by time diagrams of binary signals at the terminals of
the circuits. An estimate of the required FPGA resource costs is given, expressed in the number of
logical elements and user contacts. Also, using the example of low integration devices and the
most resource-intensive samples, the upper and lower estimates of the number of FPGAs of various
types of the Xilinx Spartan-6, Xilinx Virtex-4 families and the domestic 5576/5578 series of
JSC KTC Electronics are given. It is established that with the number of diagnostic sensors up to
200, depending on the FPGA family, up to 17 low integration chips and up to 7 resource-intensive
chips are required to implement one monitoring polling device.
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