SCALING OF INTEGER DATA IN RECONFIGURABLE COMPUTER SYSTEMS WHEN CALCULATING A RADAR RANGE-VELOCITY PORTRAIT

Abstract

This article deals with the question of preventing overflows of the bit grid in highperformance
reconfigurable computing systems based on FPGAs, leading to fatal data processing
errors when obtaining a radar range-velocity portrait of the target. The known methods of solving
this problem are briefly considered. A new method for a priori determination of the number of
scaling points in pipeline-parallel computing structures that form the target's radar range-velocity
portrait is proposed. This technique allows to determine in advance the required number of scaling
points at all stages of integer data processing and to prevent overflows when calculating theFFT (IFFT) in all possible situations. An algorithm of forming of range-velocity portrait from an
initial signal matrix is considered by the example of a continuous-wave radar system with linear
frequency modulation (LFM). Formulas for calculating the maximum value of the amplitude of the
converted signals at all stages of obtaining the range-velocity portrait and the number of iterations
with scaling in the FFT (IFFT) procedures are given. A numerical example of calculating the
number of scaling points for all stages of the algorithm of range-velocity portrait formation is
presented. In the example the required number of iterations with scaling is determined when calculating
the fast convolution and Doppler velocity (taking into account multiplication by the window
function). It allows to prevent signal values from going beyond the bounds of the bit grid. As a
result, it was found that the proposed method for calculating the number of scaling points avoids
an excessive drop in the signal level at the processing output and reduces the ratio of digital processing
errors to the signal level of the range-velocity matrix.