HARDWARE-ORIENTED ALGORITHM OF A QUATERNION CRYPTOSYSTEM
Abstract
The need to protect information provided in electronic form, due to the process of global computerization. The most common way to protect information is the use of cryptographic meth-ods, namely, data encryption algorithms. Currently, the development of information technology focuses on increasing the computing power of computers, which adversely affects the cryptograph-ic strength of most existing information protection algorithms - this is the reason for the continu-ous activity in the field of creating and improving cryptographic systems. Due to the fact that the hardware implementation of the cryptographic algorithm ensures its integrity, and also allows increasing the speed of data processing, the purpose of the work was to develop an algorithm ori-ented to the hardware implementation. The analysis shows that block ciphers with matrix multipli-cation are promising in this direction. Therefore, the matrix quaternion cipher R4 was taken as the source algorithm, since its multiplication process is based on matrix multiplication, which ensures ease of implementation and high performance. Also, this algorithm is chosen because it uses qua-ternions to create key-matrices, which allow generating direct and inverse matrices without signif-icant costs, which reduces the number of necessary computational operations for encryption and decryption, since this cryptographic algorithm is symmetric. The study is aimed at finding a matrix of this type, in which only the addition and shift operations will be used in encryption and decryption. The article describes the obtained HW-R4 algorithm, the principles of its hardware implementation, and also compares it with the existing matrix quaternionic algorithms by the characteristics of irreg-ular deviations, the correlation coefficient, and also by a visual representation of the encrypted im-ages and function graphs. Further development of the algorithm is possible in its immediate hard-ware implementation, for example, by using a programmable logic integrated circuit.
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