LOGICAL RESYNTHESIS OF COMBINATIONAL CIRCUITS FOR RELIABILITY INCREASE
Abstract
The external influences are necessary to take into account for microelectronic devices operating
in space. In these conditions, the operation of the device is hampered by the negative
effect of radiation on the electronic components of the circuit. Exposure of heavy charged part icles
leads to single faults of logic elements due to which the operation of a whole device can be
violated. In this regard, the designed spacecraft electronic circuits must meet increased r equirements
for the fault tolerance of integrated circuits (ICs). The decrease of technological
design standards for ICs makes the problem of fault tolerance to be relevant for civilian microelectronic
products, also. The solution to this problem is usually carried out by methods of
hardware protection, which include methods of error-correcting coding, methods of redundancy,
as well as methods of logical protection. The paper considers the methods for assessing the
IC tolerance to single faults in logic elements, as well as the main methods of circuits failure
protection. The paper proposes a resynthesis technique for logical combinational circuits, using
logical constraints derived from the resolution method to assess the IC resistance to single faults.During resynthesis, it is proposed to use the methods of logical protection of vulnerable parts of
the circuit. This does not cause a perceptible increase in the area occupied by the device unlike in
methods of redundancy and error-correcting coding.
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