AUTOMATIC PLACING OF SYNCHRONIZATION FLIPFLOPS DURING PARALLEL PROGRAMS SYNTHESIS FOR RECONFIGURABLE COMPUTER SYSTEMS
Abstract
At present, one of the problems of application implementation in the field of programmable gate arrays is edge-triggered clocking for stable operation of computing circuits. The existing approaches to solution of the problem have several shortcomings; they require larger hardware resource or significantly increase the design time. For efficient solution of this problem, it is nec-essary to combine advantages of existing CADs (a guaranteed solution, obtained in tight time limits) in one method, and avoid their shortcomings. In the paper we consider implementability of such method of automatic placing of synchronization flipflops. The suggested method is based on accounting of the maximal fanout coefficient at placing of synchronization flipflops, because the existing CAD-tools are not capable to synthesize tasks with the high fanout coefficient, when a chip is filled up to 80–90 %. The main purpose of the developed method is keeping balance be-tween stable operation of a circuit and optimization of occupied hardware, which is required for edge-triggered clocking. The suggested method was implemented as a part of the multichip synthe-sizer of circuit solutions Fire!Constructor, which in its turn is a part of the COLAMO development environment, used for creation of efficient parallel applications. Their performance is close to the performance of solutions, designed with the help of architecture description languages. We esti-mated the efficiency of the obtained solution with the help of tasks from such problem domains as linear algebra, digital signal and symbolic processing. Owing to application of the suggested method, we obtained solutions which were successfully wired by the Xilinx Vivado 2018.2 CAD tools for the frequency range from 250 to 400 MHz. Our research has shown, that application of the developed method provides decreasing of the development time and the debugging time for RCS applications from several days (2–3 days, required for re-translation of designed solutions by CAD-tools because of manual placing of synchronization flipflops) to several minutes (1–2). In this case, the total hardware resource exceeds the resource, occupied by manual (suboptimal) placing, not more than by 5 %.
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