THE METHOD OF ARCHITECTURALLY INDEPENDENT HIGH-LEVEL SYNTHESIS OF VLSI
Keywords:
Parallel computing, data flow, functional programming, VLSI, high-level synthesis, Archi-tecture-Independent Parallel Programming
Abstract
The problem of high-level design of complex functional circuits and systems intended for implementation in the form of VLSI is considered. The basic shortcomings of existing approaches are revealed and a conceptually new method of project synthesis is proposed. The method is based on the functional-streaming paradigm of parallel computing, it allows for implementation of an architecture-independent development of algorithms for VLSI operation. A computation model is proposed that uses a number of intermediate structures, namely, control, information, and HDL graphs. The requirements for the language of functional-streaming programming and, taking into account the specifics of the tasks to be solved, the language is selected and modified. The descrip-tion of the key points in the semantics of the language, the principles of parallelism transformation and the formation of intermediate representations in the transition to the target platform are given. The route and algorithm of high-level synthesis has been developed. The basic requirements for the creation of architecture-independent tools are identified, software tools are implemented, and a number of test projects are executed.
References
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3. Dennis McCain, Tejas M. Bhatt. Matlab as a Development Environment for FPGA Design, Design Automation Conference, Proceedings 42nd – 2005.
4. Bailey B., Martin G., Piziali A. ESL Design and Verification, ESL Des. Verif., 2007, pp. 113-138.
5. Bhasker J. A SystemC Primer. 2nd ed. Star Galaxy Publishing, 2004.
6. Vivado Design Suite User Guide. High-Level Synthesis. UG902 – Xilinx – 2015. Available at: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug902-vivado-high-level-synthesis.pdf , свободный (accessed 08 May 2018).
7. Ejnioui A., Namballa R., Ranganathan N. Control and data flow graph extraction for high-level synthesis, VLSI Proceedings. IEEE Computer society Annual Symposium on, 2004, pp. 187-192.
8. Alves C., Ferreira P., Ferreira C. Erlang inspired Hardware, International Conference on Field Programmable Logic and Applications, Milano – 2010.
9. Mycroft A., Sharp R. Hardware/software co-design using functional languages, Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS ’01), 2001, pp. 236-251.
10. Dongarra J., Bosilca G., Bouteiller A., Danalis A., Faverge M., Herault T. PaRSEC: A pro-gramming paradigm exploiting heterogeneity for enhancing scalability, IEEE Computing in Science and Engineering, 2013, Issue 6, Vol. 15, pp. 36-45.
11. Danalis A., Bosilca G., Bouteiller A., Herault T., Dongarra J. PTG: An Abstraction for Un-hindered Parallelism, Proceedings of the Fourth International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing, 2014, pp. 21-30.
12. Legalov A.I. Funktsional'nyy yazyk dlya sozdaniya arkhitekturno-nezavisimykh parallel'nykh programm [Functional language for creation of architecture-independent parallel programs], Vychislitel'nye tekhnologii [Computation Technologies], 2005, No. 1 (10), pp. 71-89.
13. Bian Jinian, Wu Quang, Wang Yunfeng, Wu Weimin. A hierarchical CDFG as Intermediate Representation for Hardware/Software Codesign, Communications, Circuits and systems and West Sino Expositions, IEEE 2002 International Conference, 2002, Vol. 2, pp. 1429-1432.
14. Levin I.I., Dordopulo A.I., Pisarenko I.V., Mel'nikov A.K. Podkhod k arkhitekturno-nezavisimomu programmirovaniyu vychislitel'nykh sistem na osnove aspektno-orientirovannogo yazyka SET@L [Approach to architecture-independent programming of computer systems in aspect-oriented SET@L language], Izvestiya YuFU. Tekhnicheskie nauki [Izvestiya SFedU. Engineering Sciences], 2018, No. 3 (197), pp. 46-58.
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17. Narasimhan M., Ramanujam J. A fast approach to computing exact solutions to the resource-constrained scheduling problem, ACM TODAYES, 2001, Vol. 6 (4), pp. 490-500.
18. Amellal S., Kaminska B. Scheduling of a control and data flow graph, IEEE Int. Symp. on Cir-cuits and Systems, 1993, Vol. 3, pp. 1666-1669.
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20. Nepomnyashchiy O.V., Legalov A.I., Ryzhenko I.N. Tekhnologiya arkhitekturno-nezavisimogo, vysokourovnevogo sinteza sverkhbol'shikh integral'nykh skhem [Technology of architec-ture-independent, high-level synthesis of ultra-large integrated circuits], Doklady Akademii nauk vysshey shkoly Rossiyskoy Federatsii [Reports of the Academy of Sciences of the higher school of the Russian Federation], 2014, No. 1 (22), pp. 93-103.
Published
2019-04-03
Issue
Section
SECTION I. PRINCIPLES OF CONSTRUCTION OF HIGH-PERFORMANCE COMPUTING SYSTEMS
