FLOATING–POINT ADDER IN DIGITAL PHOTONIC COMPUTING SYSTEMS

Abstract

Within the structural computation paradigm proposed by the authors, digital photonic computing systems are expected to employ sequential data processing, which allows for the minimization of operand duty cycle gaps when data is supplied from external memory or other electronic sources to the photonic device. This becomes feasible when the processing time per operand does not exceed the number of clock cycles corresponding to the operand’s bit width. Moreover, sequential digit–wise processing significantly reduces hardware costs associated with dataflow synchronization. The elimination of duty cycle gaps and reduction in structural overhead can substantially enhance the efficiency of digital photonic computing systems relative to their electronic counterparts. However, to enable photonic computational architectures capable of solving complex and computation–intensive problems in domains such as mathematical physics, linear algebra, neural network processing, and others, it is necessary to implement core arithmetic functions in floating–point format. Most of these functions are built around elementary integer addition. In binary systems with sequential processing in least–significant–digit–first order, integer adders are unable to begin producing results until all bits have been processed and carry propagation is complete, thereby doubling the operand duty cycle and increasing latency. To address these issues, this paper proposes the use of a quaternary signed–digit number representation with operands processed in most–significant–digit–first order. This representation enables immediate transmission of the most significant digits of the result to downstream processing units, without waiting for the completion of lower–order digit computation. This paper addresses the design of all components of the signed–digit floating–point adder: the exponent difference unit, the mantissa denormalization unit for the operand with the smaller exponent, the mantissa adder, the mantissa normalization unit for the result, and the exponent correction unit. Operational algorithms for these units are presented. The performance of the proposed signed–digit adder has been evaluated on a prototype implemented in a digital photonic logic framework on the reconfigurable “Terzius” computing platform. It is demonstrated that, due to the high clock frequency achievable by digital photonic computing devices, their performance can exceed that of microelectronic devices by nearly two orders of decimal scale.