FEATURES OF LOW-VOLTAGE DIGITAL CIRCUITS BASED ON CMOS TECHNOLOGIES 90–20 NM
Abstract
To increase energy efficiency, CMOS integrated circuits use a subthreshold mode of operation. The supply voltage decreases to a level lower than the threshold voltages of the MOSFETs, currents decrease and performance decreases. However, often a reduction in power consumption is more important than low performance. Therefore, CMOS integrated circuits in the subthreshold mode have applications where a radical reduction in power consumption is a crucial requirement. Now firms have used technologies with minimum sizes from 500 to 3 nm, with most of the products being at the 90–20 nm. The paper analyzes low-voltage circuits based on technologies 90–20 nm to develop recommendations for the design of energy-efficient devices. A technique for determining the key parameters of predictive MOSFET models in the subthreshold mode is considered. Expressions of the characteristics of inverter in the subthreshold region are obtained. Analysis shows a significant deterioration in the characteristics of CMOS elements in the subthreshold mode with a decrease in the dimensions of less than 90 nm. It is explained that when developing technology 90–20 nm, all measures were aimed at reducing leakage currents in the over threshold mode to reduce static power consumption. To improve the characteristics of CMOS elements in the subthreshold mode, it is necessary to optimize the design and technology to reduce the values of the subthreshold span, the DIBL coefficient and increase the characteristic current. The results may be useful for developers of energy-efficient equipment.
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