Search

Search Results

• ANALYSIS OF CHARACTERISTIC FOR CED CIRCUITS BASED ON REDUNDANT ENCODING METHODS

  D. V. Telpukhov , T. D. Zhukova, A. N. Schelokov

  2020-11-22

  Abstract ▼

  Typically, soft errors that occur in electronic equipment under influence of various destabilizing
  factors, were under the scrutiny of memory element developers. But recent research in this
  area shows that with development of microelectronics, the number of soft errors in combination
  circuits is increasing and soon their frequency of occurrence will be comparable to that in unprotected
  memory elements. Presently, to address this problem, special attention has been paid to
  methods based on control devices. These methods, by introducing additional structural redundancy,
  enable scheme to automatically detect and/or correct errors that occur in it. However, as a
  result of application of various methods of synthesis concurrent error detection (CED) circuits
  depending on initial parameters and internal structure of protected scheme devices possessing
  various efficiency and reliability characteristics are realized. However, as a result of application
  of various methods of synthesis CED circuits depending on initial parameters and internal structure
  protected circuit, the devices possessing different efficiency and reliability characteristics are
  realized. That is why there is a necessity to define and develop evaluation functions for analysis inorder to find the best method of synthesis CED circuit for certain device without any preliminary
  modeling. This work is devoted to development specification of structural redundancy and reliability
  characteristics evaluation functions on the example of CED circuits on basis of spectral and lowdensity
  parity-check code. The comparative and correlation analysis of analytical data with experimental
  values was carried out to evaluate efficiency of the functions obtained as a result of study.

• LOGICAL RESYNTHESIS OF COMBINATIONAL CIRCUITS FOR RELIABILITY INCREASE

  N. O. Vasilyev , M.A. Zapletina , G. A. Ivanova , A.N. Schelokov

  2020-11-22

  Abstract ▼

  The external influences are necessary to take into account for microelectronic devices operating
  in space. In these conditions, the operation of the device is hampered by the negative
  effect of radiation on the electronic components of the circuit. Exposure of heavy charged part icles
  leads to single faults of logic elements due to which the operation of a whole device can be
  violated. In this regard, the designed spacecraft electronic circuits must meet increased r equirements
  for the fault tolerance of integrated circuits (ICs). The decrease of technological
  design standards for ICs makes the problem of fault tolerance to be relevant for civilian microelectronic
  products, also. The solution to this problem is usually carried out by methods of
  hardware protection, which include methods of error-correcting coding, methods of redundancy,
  as well as methods of logical protection. The paper considers the methods for assessing the
  IC tolerance to single faults in logic elements, as well as the main methods of circuits failure
  protection. The paper proposes a resynthesis technique for logical combinational circuits, using
  logical constraints derived from the resolution method to assess the IC resistance to single faults.During resynthesis, it is proposed to use the methods of logical protection of vulnerable parts of
  the circuit. This does not cause a perceptible increase in the area occupied by the device unlike in
  methods of redundancy and error-correcting coding.

• APPLICATION OF THE HAMMING CODE IN THE PROBLEM OF INCREASING FAULT TOLERANCE OF LOGIC CIRCUITS

  D.V. Telpukhov , T.D. Zhukova, A.N. Schelokov, P.D. Kretinina

  2021-11-14

  Abstract ▼

  Currently, when designing integrated circuits, developers have to take into account a very
  large number of dissimilar factors that are associated with ensuring the necessary performance
  characteristics, occupied area, energy efficiency, yield, convenience of subsequent testing, requirements
  for universality, autonomy, and so on. One of the main factors is the reliability of operation.
  This criterion comes to the fore for critical applications, as well as for devices operating
  under the influence of destabilizing factors. To provide increased reliability, different methods and
  approaches are used at different levels of abstraction. Some of them can be applied at the design
  stage. One of the main methods for improving the reliability of integrated circuits at the design
  stage is the use of tools from the theory of error-correcting coding.The traditional field of application
  of error-correcting codes is the control of the integrity of stored and transmitted information.
  Combinational logic circuits, on the other hand, change information and do not have storage elements.
  Combinational logic circuits implement look-up tables at the gate level, which unambiguously
  assign a certain output value to each input action. Nevertheless, the use of error-correcting
  codes for constructing error-tolerant combinational circuits turns out to be very effective. This
  requires the introduction of additional combinational blocks into the circuit, which provide coding,
  decoding, control, and in some cases correction of errors arising in the circuit. The paper
  investigates the efficiency of using Hamming codes in relation to the construction of fault-tolerant
  combinational circuits. The paper considered classical Hamming code and his main modification -
  weighted code with summation without carries for the implementation of fault-tolerant combinational
  circuits. Means have been developed for the automated synthesis of fault-tolerant circuits
  based on these codes. Structural redundancy and reliability characteristics of the resulting circuits
  are investigated. Comparison with traditional method triple modular redundancy is carried out.
  Estimating functions are derived for redundancy and the probability of missing an error.