ANALYSIS OF CHARACTERISTIC FOR CED CIRCUITS BASED ON REDUNDANT ENCODING METHODS

Abstract

Typically, soft errors that occur in electronic equipment under influence of various destabilizing factors, were under the scrutiny of memory element developers. But recent research in this area shows that with development of microelectronics, the number of soft errors in combination circuits is increasing and soon their frequency of occurrence will be comparable to that in unprotected memory elements. Presently, to address this problem, special attention has been paid to methods based on control devices. These methods, by introducing additional structural redundancy, enable scheme to automatically detect and/or correct errors that occur in it. However, as a result of application of various methods of synthesis concurrent error detection (CED) circuits depending on initial parameters and internal structure of protected scheme devices possessing various efficiency and reliability characteristics are realized. However, as a result of application of various methods of synthesis CED circuits depending on initial parameters and internal structure protected circuit, the devices possessing different efficiency and reliability characteristics are realized. That is why there is a necessity to define and develop evaluation functions for analysis inorder to find the best method of synthesis CED circuit for certain device without any preliminary modeling. This work is devoted to development specification of structural redundancy and reliability characteristics evaluation functions on the example of CED circuits on basis of spectral and lowdensity parity-check code. The comparative and correlation analysis of analytical data with experimental values was carried out to evaluate efficiency of the functions obtained as a result of study.