The purpose of this work is to estimate the time costs for multiplying square binary matrices of size n × n by a device with pipelining the operation of reading data from a specialized multiport memory and compare it with the time costs of the prototype. This work used methods of mathematical logic, set and graph theory, discrete systems and computer devices, and finite state machine design theory. As a result of the study, it was shown that the use of pipelining the operation of reading data from specialized multiport memory reduces the time spent on processing square binary matrices with a size of n ≤ 2048 up to 206.3 times. It can be seen from the data obtained that the loading and unloading time of the source and result data for the proposed device is significantly higher than the matrix multiplication time, which makes frequent loading and unloading of matrices impractical. For example, when performing the operation of transitive closure of a binary relation represented as a binary matrix, the initial matrix is loaded once, followed by a series of squaring, which is effectively implemented by the proposed device. Based on the obtained results, it can be concluded that the proposed device for multiplying square binary matrices with
