Skip to main content Skip to main navigation menu Skip to site footer
##common.pageHeaderLogo.altText##
Izvestiya SFedU
Engineering sciences
  • Current
  • Previous issues
    • Archive
    • Issues 1995 – 2019
  • Editorial Board
  • About journal
    • Officially
    • The main tasks
    • Main sections
    • Specialties of the Higher Attestation Commission of the Russian Federation
    • Editor-in-Chief
ISSN 1999-9429 print
ISSN 2311-3103 online
  • Login
  1. Home /
  2. Search

Search

Advanced filters
Published After
Published Before

Search Results

##search.searchResults.foundPlural##
  • DESCRIPTION OF GRAPHS WITH ASSOCIATIVE OPERATIONS IN SET@L PROGRAMMING LANGUAGE

    I. I. Levin , I. V. Pisarenko, D. V. Mikhailov , A. I. Dordopulo
    2020-10-11
    Abstract ▼

    Usually, an information graph with associative operations has a sequential (“head/tail”) or
    parallel (“half-splitting”) topology with invariable quantity of operational vertices. If computational
    resource is insufficient for the implementation of all vertices, the reduction transformations
    of graphs with basic topologies do not allow for the creation of an efficient resource-independent
    program. In fact, the “half-splitting” variant is characterized by irregular connections between
    iterations, and the “head/tail” structure has an increased data duty cycle in the reduced form.
    In this paper, we propose to transform the topology of a graph with associative operations into a
    combined variant with sequential and parallel fragments of calculations. The resultant combined
    topology depends on computational resource of a parallel computer system, and such transformation
    provides the improvement of specific performance for the reduced computing structure.
    The considered topology contains isomorphic subgraphs with the “half-splitting” topology, which
    include the maximal number of hardwarily implemented operational vertices, but the processing of
    intermediate data is performed using the “head/tail” principle. The computing structure for the
    combined topology has minimal latency and includes one basic subgraph and one vertex with
    feedback. This vertex is obtained as a result of the “head/tail” block reduction. We develop an
    algorithm for the conversion of the initial sequential graph to various combined topologies or to
    the limiting case of the “half-splitting” topology with regard to available hardware resource.
    Within traditional methods of parallel programming, it is possible to describe the variety of topologies
    only as a set of separated subprograms. To create an efficient resource-independent program,
    we propose the application of the Set@l programming language. We describe the
    “head/tail” and “half-splitting” principles as the attributes of set processing methods in Set@l.
    Resource-independent program uses these types and parallelism attributes for the modification of
    topology and further reduction of performance in the corresponding aspects.

  • HIGH-LEVEL TOOLS FOR TRANSLATION OF C-APPLICATIONS INTO APPLICATIONS IN DATAFLOW LANGUAGE COLAMO

    A.I. Dordopulo, A.A. Gulenok, A.V. Bovkun, I.I. Levin, V.A. Gudkov, S.A. Dudko
    2021-02-25
    Abstract ▼

    In the paper we review software tools for translation of sequential C-programs into scalable
    parallel-pipeline programs written in the COLAMO language, used for programming of reconfigurable
    computer systems. In contrast to existing tools of high-level synthesis, the translation result
    is not an IP-core of a task fragment, but a complex task solution for multichip reconfigurable
    computer systems with automatic synchronization of data and control signals. We analysed the
    main translation steps of a sequential C-program such as transformation into an information
    graph, analysis of data dependencies and selection of functional subgraphs, transformation into a
    scalable resource-independent parallel-pipeline form, and scaling a COLAMO-program for a
    specified multichip reconfigurable computer system. A program is scaled with the help of performance
    reduction methods, applied to a completely parallel form of a task (an information graph),
    adapted to the architecture of a reconfigurable computer system. We developed several rules,significantly reducing the number of transformation steps of task scaling, and providing a continuous flow of data processing in the functional subgraphs of the task. The developed software tools
    for translation of C-programs into FPGA configuration files significantly decrease the synthesis
    time of a task computing structure for multichip RCSs and the total task solution time.

1 - 2 of 2 items

links

For authors
  • Submit article
  • Author Guidelines
  • Editorial Policy
  • Reviewing
  • Ethics of scientific publications
  • Open access policy
  • Supporting documents
Language
  • English
  • русский

journal

* not an advertisement

index

Индексация журнала
* not an advertisement
Information
  • For Readers
  • For Authors
  • For Librarians
Address: 347900, Taganrog, Chekhov St., 22, A-211 Phone: +7 (8634) 37-19-80 E-mail: iborodyanskiy@sfedu.ru
Publication is free
More information about the publishing system, Platform and Workflow by OJS/PKP.
logo Developed by RDCenter