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• APPLICATION OF THE HAMMING CODE IN THE PROBLEM OF INCREASING FAULT TOLERANCE OF LOGIC CIRCUITS

  D.V. Telpukhov , T.D. Zhukova, A.N. Schelokov, P.D. Kretinina

  2021-11-14

  Abstract ▼

  Currently, when designing integrated circuits, developers have to take into account a very
  large number of dissimilar factors that are associated with ensuring the necessary performance
  characteristics, occupied area, energy efficiency, yield, convenience of subsequent testing, requirements
  for universality, autonomy, and so on. One of the main factors is the reliability of operation.
  This criterion comes to the fore for critical applications, as well as for devices operating
  under the influence of destabilizing factors. To provide increased reliability, different methods and
  approaches are used at different levels of abstraction. Some of them can be applied at the design
  stage. One of the main methods for improving the reliability of integrated circuits at the design
  stage is the use of tools from the theory of error-correcting coding.The traditional field of application
  of error-correcting codes is the control of the integrity of stored and transmitted information.
  Combinational logic circuits, on the other hand, change information and do not have storage elements.
  Combinational logic circuits implement look-up tables at the gate level, which unambiguously
  assign a certain output value to each input action. Nevertheless, the use of error-correcting
  codes for constructing error-tolerant combinational circuits turns out to be very effective. This
  requires the introduction of additional combinational blocks into the circuit, which provide coding,
  decoding, control, and in some cases correction of errors arising in the circuit. The paper
  investigates the efficiency of using Hamming codes in relation to the construction of fault-tolerant
  combinational circuits. The paper considered classical Hamming code and his main modification -
  weighted code with summation without carries for the implementation of fault-tolerant combinational
  circuits. Means have been developed for the automated synthesis of fault-tolerant circuits
  based on these codes. Structural redundancy and reliability characteristics of the resulting circuits
  are investigated. Comparison with traditional method triple modular redundancy is carried out.
  Estimating functions are derived for redundancy and the probability of missing an error.