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• DESIGNING MLP AND CNN NEURAL NETWORK MODULES ON FPGA FOR IMAGE CLASSIFICATION TASKS

  E. V. Melnik , D.Е. Blokh , А.I. Bezmeltsev , V.S. Panishchev , S.N. Poltoratsky

  214-229

  2025-11-10

  Abstract ▼

  Relevance. The development of machine learning methods and neural network architectures, as well as their spread into various industrial sectors, determine the relevance of solving problems related to their hardware implementation. The use of programmable logic integrated circuits in this area will increase data processing speed and the adaptability of the implemented algorithms. However, designing neural network architectures on programmable logic integrated circuits is associated with a number of methodological and technical difficulties, including the optimization of parallel computing, hardware resource management, and ensuring operation under conditions of limited computing resources. The purpose of this work is to analyze and compare two neural network architectures, the multilayer perceptron (MLP) and the convolutional neural network (CNN), in the context of their hardware implementation on programmable logic integrated circuits (PLICs). Particular attention is paid to the trade-off between classification accuracy and the efficient use of limited FPGA hardware resources. Research methods.
  To achieve the goal, two modules were developed and simulated on a Virtex 7 FPGA, a perceptron and a convolutional module. The MNIST dataset, reduced to 20×20 pixels, was used. The implementation included quantizing parameters to a fixed 16:16 format, optimizing hyperparameters, using tabular computations for nonlinear functions, and evaluating FPGA resource usage. Results and discussions.
  MLP achieved 93% accuracy using 11% of logic elements, while CNN achieved 98% accuracy but required significantly more resources. The use of internal buffers to store intermediate data in CNN resulted in exceeding the allowable resources. The forced transition to external memory increased delays and the number of I/O ports. Conclusions. The study showed that the choice of architecture depends on priorities: CNN provides better accuracy but is less resource-efficient. For embedded systems with memory and power consumption constraints, a simplified MLP implementation is preferable. The main problems remain the lack of internal memory and the high resource intensity of operations, which requires further research in the field of hardware optimization and adaptive computation control

• USING FAST PROTOTYPING FACILITIES FOR IMPLEMENTATION OF A CONVOLUTION NEURAL NETWORK ON A FPGA

  V. V. Bakhchevnikov , V. A. Derkachev , A. N. Bakumenko

  2020-10-11

  Abstract ▼

  Research in the field of artificial intelligence is carried out with increasing interest every
  year. The fields of application of artificial intelligence are quite extensive: automation, analysis of
  a large amount of data, smart home technology, machine vision, etc. Artificial intelligence technologies
  are based on the use of artificial neural networks, which are based on the principles of
  the animal nervous system. In this case, the actual issue is the implementation of artificial neural
  networks on various software and hardware platforms: programmable logic integrated circuits of
  the FPGA type (Field Programmable Gate Array), on special purpose integrated circuits (Application-
  Specific Integrated Circuit, ASIC), GPU, CPU etc. FPGA performs best in low-power mobile
  systems. ASIC demonstrates the highest performance at a fairly high development cost.
  The problem of rapid prototyping of projects based on the use of artificial neural networks for
  FPGAs using conventional methods (using HDL languages, HDL encoders, graphic programming)
  is that either such a project is complex and time-consuming to debug (HDL languages), or
  the resulting code is not optimal (HDL encoders), or the duration of the project development and
  the complexity of reconfiguring the neural network (graphical programming) are high. Therefore,
  in the framework of this work, an effective method for designing fully connected and convolutional
  neural networks for their implementation on FPGAs using the Xilinx System Generator for DSP
  and Matlab / Simulink package is considered. Artificial neural networks generated in this way are
  easily reconfigurable and allow solving the following problems: image recognition, optimal filtering
  (for example, for problems of subsurface radar).

• A METHOD FOR SOLVING GRAPH NP-COMPLETE TASKS ON RECONFIGURABLE COMPUTER SYSTEMS BASED ON THE ITERATION PARALLELIZING PRINCIPLE

  A.V. Kasarkin

  2021-02-25

  Abstract ▼

  When we solve graph NP-complete tasks on multiprocessor systems, the growth of hardware
  resource does not lead to the proportional increase of the system performance, and hence, the task
  solution time is not always reasonable. The aim of our research, given in the paper, is minimization
  of the solution time of the task of maximal clique enumeration on reconfigurable computer
  systems (RCS). When we solve tasks on RCSs with the help of the method of parallelizing by layers,
  the growth of performance also slows down in spite of better scalability in comparison with
  multiprocessor implementations. In the paper, we suggest a method of parallel-pipeline application
  development for reconfigurable computer systems. The method is based on parallelizing bylayers for graph NP-complete tasks. We show that the bit representation of sets, which is used for
  the method of parallelizing by layers, is not efficient for the method of parallelizing by iterations.
  The new method has another organization of calculations; it processes unordered sets, whose
  elements are accessed not by addresses (as in arrays), but by values (names of vertices and names
  of edges of the graph). We show that the new method, based on parallelizing by iterations, provides
  ramping of the RCS real performance at much larger computational resource in comparison
  with the method of parallelizing by layers. Its specific performance is lower, because computing
  substructures are to process more intermediate data due to symbolic representation of sets.