N. O. Vasilyev , P.I. Frolova , G.A. Ivanova , A. N. Schelokov
2020-11-22
Abstract ▼
As the size of electronic components decreases, the number of design rules increases. To reduce design rules checking runtime for 22 nm and below technologies, regular structures are used in the lower layers of the layout. When designing circuits based on a regular template, it becomes possible to combine the logical and layout design stages. This task is also relevant for designing circuits on FPGAs. This paper discusses a method for structural optimization of logic circuits at the stage of layout design. The method is adapted for use in the design route of circuits with regular structures in the lower layers of the layout, as well as for resynthesis of technology mappings on FPGAs. When working with circuits with regular structures, logical synthesis is used in the basis of elements for which compact layout templates are built. This approach simplifies the layout design stage, and also leads to an additional reduction in the area of the designed device. Optimization of logic circuits for FPGAs is carried out using a simulated annealing algorithm that performs logic operations on a special graph model that takes into account the features of the FPGA. Taking into account the features of various technologies in the proposed method allows achieving good results in terms of such parameters as the area occupied by the circuit.
