The purpose of this paper is to improve the efficiency of pseudo-random testing of digital devices compared to the conventional approach. To achieve this goal, the following main tasks are solved in the work: analysis of the effectiveness of traditional testing approaches; developing a new approach based on recognition and adaptive pseudo-random testing of digital devices and developing a testing system based on the proposed approaches and conducting experimental studies based on it. The devices under test in this paper are sequential digital devices (with memory elements), implemented as printed circuit board on microcircuits with medium and small degree integration. Stuck-at faults are used as fault models in test synthesis and analysis. The subject of this research is sequential digital devices as diagnostic objects and approaches to their pseudo-random testing. An approach to recognizing and testing sequential digital devices is presented, which is based on a combination of traditional pseudo-random testing device under test at the first stage with and constructing an "alternative graph" of the device at the second stage and subsequent "wandering" along this graph in order to improve the testing efficiency. Based on the proposed approach a system AGAT for recognizing and testing digital devices has been developed. Testing can be performed for one or a group of devices under test on one computer or as part of a local computer network, including taking into account "multithreading" based on multi-core processors of personal computers in the network. Extensive research of the proposed approach and the developed system is carried out on two types of devices under test: the ISCAS'89 and the set of PCBs of the specialized radio engineering system.
