A scheme for buffering Ethernet packets for hardware implementation of their processing based on FPGA has been developed. The scheme is designed at the RTL level in the System Verilog language in the Quartus II 13.1 development environment. Verification and modeling were carried out in the ModelSim Altera environment. An FPGA of the CycloneIV family, located on the A scheme for buffering Ethernet packets for hardware implementation of their processing based on FPGA has been developed. The scheme is designed at the RTL level in the System Verilog language in the Quartus II 13.1 development environment. Verification and modeling were carried out in the ModelSim Altera environment. An FPGA of the CycloneIV family, located on the DE2-115 debugging board, was chosen as the target platform. Particular attention is paid to data reception and transmission modules, as well as the implementation of a hardware queue (FIFO) with the possibility of changing its contents by the processing module. The scheme is parameterized, it allows you to change the queue depth at the expense of one parameter without making changes to other parts of the scheme. A feature of the scheme is the ability to add any hardware module that monitors, processes or encrypts network traffic. The MII interface is used for transmitting and receiving packets, which allows using any available physical layer chips for receiving and transmitting packets. The device allows you to easily change the input and output interface, which increases its versatility. The system does not use proprietary IP cores, which makes it as portable as possible to FPGAs from various manufacturers. The main feature of the scheme is the low delay between receiving and sending a packet, determined only by the parameters of the processing module. The results of the work can be applied during the design of devices that transmit data with preprocessing. For example, network equipment (switches, routers), monitoring and data collection systems.
