A significant drawback of classical output stages of microelectronic operational amplifiers, which today are implemented based on BJTs (bipolar junction transistors), CMOS (complementary metal-oxide-semiconductor transistors), or JFETs (junction field-effect transistors), including when these technologies are used together, is that they exhibit a relatively low output voltage slew rate under the influence of large-amplitude pulsed input signals. This undesirable effect is mainly caused by the presence of parasitic capacitances inherent in the reference current source circuits employed and in their output transistors. This paper discusses an original and effective circuit design technique that provides forced recharging of parasitic capacitances, which is used in output stages implemented in numerous patents of the world’s leading microelectronic companies. The introduction of a special differentiating transient correction circuit into the original schematics, as well as various options for its practical implementation, are considered for the first time. The circuitry of such output stages is protected by a patent of the Russian Federation. Four different modifications of buffer amplifiers have been developed and investigated, which are intended for use in modern technological processes implemented with silicon BJT or CMOS transistors, as well as with gallium arsenide n-JFET and p-n-p bipolar transistors. Examples of computer simulation of DC operating modes, as well as transient processes, are presented, which clearly demonstrate a significant increase in the maximum output voltage slew rate (by more than one to three orders of magnitude). The proposed advanced circuit solutions for GaAs transistors are recommended for practical application in microelectronic devices designed for operation under elevated temperature conditions.
To increase energy efficiency, CMOS integrated circuits use a subthreshold mode of operation. The supply voltage decreases to a level lower than the threshold voltages of the MOSFETs, currents decrease and performance decreases. However, often a reduction in power consumption is more important than low performance. Therefore, CMOS integrated circuits in the subthreshold mode have applications where a radical reduction in power consumption is a crucial requirement. Now firms have used technologies with minimum sizes from 500 to 3 nm, with most of the products being at the 90–20 nm. The paper analyzes low-voltage circuits based on technologies 90–20 nm to develop recommendations for the design of energy-efficient devices. A technique for determining the key parameters of predictive MOSFET models in the subthreshold mode is considered. Expressions of the characteristics of inverter in the subthreshold region are obtained. Analysis shows a significant deterioration in the characteristics of CMOS elements in the subthreshold mode with a decrease in the dimensions of less than 90 nm. It is explained that when developing technology 90–20 nm, all measures were aimed at reducing leakage currents in the over threshold mode to reduce static power consumption. To improve the characteristics of CMOS elements in the subthreshold mode, it is necessary to optimize the design and technology to reduce the values of the subthreshold span, the DIBL coefficient and increase the characteristic current. The results may be useful for developers of energy-efficient equipment.
N. O. Vasilyev , P.I. Frolova , G.A. Ivanova , A. N. Schelokov
2020-11-22
Abstract ▼
As the size of electronic components decreases, the number of design rules increases. To reduce design rules checking runtime for 22 nm and below technologies, regular structures are used in the lower layers of the layout. When designing circuits based on a regular template, it becomes possible to combine the logical and layout design stages. This task is also relevant for designing circuits on FPGAs. This paper discusses a method for structural optimization of logic circuits at the stage of layout design. The method is adapted for use in the design route of circuits with regular structures in the lower layers of the layout, as well as for resynthesis of technology mappings on FPGAs. When working with circuits with regular structures, logical synthesis is used in the basis of elements for which compact layout templates are built. This approach simplifies the layout design stage, and also leads to an additional reduction in the area of the designed device. Optimization of logic circuits for FPGAs is carried out using a simulated annealing algorithm that performs logic operations on a special graph model that takes into account the features of the FPGA. Taking into account the features of various technologies in the proposed method allows achieving good results in terms of such parameters as the area occupied by the circuit.
