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• LOGIC CELL FOR VLSI BASED ON FIELD-EFFECT TRANSISTORS WITH P-N JUNCTIONS

  P.G. Gritzaenko, L. А. Svetlichnaya

  97-106

  2025-08-01

  Abstract ▼

  In the 80s of the last century, integrated injection logic (I2L) was widely used as an element
  base. Somewhat later, injection-field logic (IPL) appeared in the development of I2L capabilities
  for building VLSI. Thanks to the use of a field-effect transistor as a key element of the inverter, in
  this element basis it was possible to significantly reduce an important indicator for VLSI – power
  consumption - reaching the peak-watt range. An even greater reduction in power consumption can
  be achieved by using two field-effect transistors in the inverter unit cell, which is proposed in this
  paper. This element basis is proposed to be called field-field logic, or in the future P2L. To reduce
  the dimensions of the P2L cell, field-effect transistors, both key and load, are made with a vertical
  channel. In addition, to ensure a positive supply voltage, an n-channel transistor is used as a key
  one, and a p–channel transistor is used as a load one. Both transistors are normally closed, i.e.
  closed at zero gate voltage. Topological variants of P2L-cell execution from geometry with annular
  gates to geometry with linear gates proposed by the author earlier are considered. The topological
  norms adopted in the consideration are the norms of 50 nm. The power consumption in this
  element basis is reduced by about two times compared to the IPL, due to the fact that the current
  flows through the load transistors in the inverter chain through one inverter, as well as through
  the key ones. The technological process of manufacturing a P2L cell is considered, the profiles of
  the distribution of impurities in depth are calculated. The manufacturing process is designed taking
  into account the fact that the load p-channel transistor must be made in an insulated pocket
  using full dielectric insulation technology. The technological modes of manufacturing the P2L cell
  are given. The proposed design and technological variant of the P2L cell can be recommended for
  the creation of VLSI with low power consumption

• INJECTION-FIELD STRUCTURE MADE BY DOUBLE DIFFUSION OF IMPURITIES

  P.G. Gritzaenko

  2023-06-07

  Abstract ▼

  In the 80s of the last century, integrated injection logic (I2L) was widely used as an element
  base. Somewhat later, in the development of I2L, injection-field logic (IPL) appeared for the construction
  of VLSI. Both element bases are close in the degree of integration on a chip. An increase in
  the degree of integration into VLSI can be achieved using self-displacement of regions, in which the
  introduction of impurities of different types is carried out using a single boundary of the masking
  material. In this paper, this principle is used to create a vertical channel of a key field-effect transistor
  of IPL logic. In a p-type epitaxial film deposited on an n+-type substrate, an n-type region with a
  depth greater than the thickness of the epitaxial film is sequentially created first, and then impurity
  diffusion is performed in the same window with the creation of a region p-type. The gap between
  these n-type regions is the channel of the field-effect transistor being formed. Next, a shallow n+-type
  region is created that overlaps the channel, which is the drain region of a key field-effect transistor
  with a vertical channel, the p-type diffusion region is a gate, and the uniformly alloyed region of the
  epitaxial film performs the function of an injector. Branching along the outlet in this IPL structure is
  provided by placing several drains along the perimeter of the channel. Due to this geometry, the
  structure has a greater reproducibility of parameters compared to the basic design of the IPL. Topological
  variants of the implementation of the IPL cell and schemes based on it are considered:
  schemes 6 OR-NOT and Dt-trigger. The proposed design and technological version of the IPL cell
  can be recommended for creating VLSI of a high degree of integration