Search

Search Results

• A HARDWARE-ORIENTED METHOD OF ACCELERATED SEARCH BY TEMPLATE BASED ON STRUCTURAL-PROCEDURAL COMPUTING

  Е. А. Titenko, E.I. Vatutin, М.А. Titenko, А.P. Loktionov, E.V. Melnik

  2024-11-10

  Abstract ▼

  The operation of searching for occurrences of a pattern in a text is generally significant in modern
  computing tools for solving problem-searching tasks. Of greatest interest are hardware and software solutions
  that have a homogeneous structure and regular connections between computing blocks. The aim of
  the work is to reduce the time costs for searching for occurrences based on the use of parallel search in
  associative memory and the method of parallelization by iterations. The proposed method uses associative
  memory for parallel search for occurrences and dynamic reconfiguration of the structure of the original
  string from a one-dimensional form to a matrix form. The method is critical to such resources as the number
  of memory access channels, the volume of block memory for creating and parallel operation of an
  array of associative cells. Involvement of all elements in the reconfiguration entails excessive costs of the
  internal block memory for sequential viewing of partial entries by one set of starting positions multiples of
  the sample length (the second symbolic operand). Instead, an approach is proposed to combine in time the
  search for partial entries by two sets of substrings multiples of the sample length, with a simultaneous
  proportional reduction in the elements of the bit slice of the associative memory for each set, which allows
  processing several sample symbols at the current search step. Quantitative estimates of search time are
  determined by the number of comparison and substring writing operations in the overall work cycle, as
  well as the proportions of the time of these operations. It is shown that for samples of more than 10 elements,
  the time gain is approximately 1.8-2 times. This effect is obtained by eliminating the steps of sequential
  shift with transitions between the boundary elements of the strings. The developed method provides
  pipeline processing of a stream of string operands with a combination of viewing at the current
  search step of a non-unit set of characters of the processed string. The search time is re duced by introducing
  a pipeline, the number of stages of which depends on the reduction coefficient of the bit slice size,
  which allows hardware implementation of the structural-procedural approach used in reconfigurable
  computing systems

• ADVANCED PRODUCTION OUTPUT ENGINE FOR IMPLEMENTING PARALLEL COMPUTING

  Е.A. Titenko, I.Е. Chernetskaya, М.А. Titenko, E.V. Melnik, D. А. Trokoz

  2024-05-28

  Abstract ▼

  Relevance. The paper discusses a theoretical approach to organizing parallel computing based on a
  production model of data flow control. The production paradigm of parallel computing has the necessary
  conditions for building new architectures and organizing high-performance parallel computing. We consider
  production (mathematical) systems that control sets of left-hand sides of productions (samples). The
  goal is to increase the efficiency of parallel inference of solutions by reducing unproductive time spent
  searching through possible alternatives in the inference graph space. The research is based on the creation
  of an extended symbolic computation machine for implementing parallel steps. A symbolic computing
  machine is an abstract system that systematizes production output as a sequence of four computational
  and search stages. The inference engine defines the general appearance of a homogeneous computing
  system. The main difference is the decomposition of the base of production rules into separate subsets
  based on the algebra of production and the structuring of relations between products. Instead of a single
  “flat” structure, it is proposed to decompose the product base into parts - to introduce a system of independent
  subsets of products. Parallel inference is implemented for individual subsets without loss of generality,
  while the search for possible alternatives is reduced. Each subset of productions has a special
  marker word, the value of which activates only one subset of productions. It is loaded into the operating
  part of a homogeneous computing system for parallel execution. Results. It is shown that quantitative
  estimates of the reduction in output time depend on the total number of productions, the number of subsets
  formed and their size. Simulation has shown that even the simplest decomposition into two subsets (one subset consists of 2 productions) gives a time gain of (1.07-1.52) times, proportional to the total number of
  productions. Conclusions. The created extended symbolic computing machine is the basis for the subsequent
  creation of the architecture of a homogeneous computing system with a combination of centralized
  and local control. This property allows computational units of a homogeneous operating part to work in
  parallel without excessive access to shared memory.

• HARDWARE-ORIENTED METHOD FOR RECONFIGURING A GROUP OF MOBILE OBJECTS

  Е.А. Titenko, I.Е. Chernetskaya, L. А. Lisitsyn, М. А. Titenko, S.I.

  2023-10-23

  Abstract ▼

  The article describes approaches and methods for managing a group of moving objects,
  characterized by the ability to autonomously make decisions about their status within the group.
  Another problem of managing such a grouping is weak predictive solutions for the connectivity of
  pairs of elements and their dependence on a single control center. Nanosatellites operating under
  conditions of uncertainty in the internal and external environment are considered as such objects.
  The goal is to ensure the coherence of the group’s apparatus through a decentralized change in
  structure. It is shown that methods and algorithms for dynamic reconfiguration of a group of moving
  objects predominantly use a centralized approach and a single ground control center, which is
  impractical for small space exploration. A class of management methods using knowledge processing
  methods and technology (artificial intelligence technology) is considered, allowing for the
  identification and use of additional information about the configuration of the group. Configuration
  is understood as a dual system that describes the composition and connections between neighboring elements with some quantitative assessment. The article checks the connectivity configuration
  of elements to ensure continuous data transfer between a pair of arbitrary grouping
  elements. The proposed reconfiguration method is hierarchical: at the upper level, reconfiguration
  is based on the principles of self-organization; at the lower level, the grouping is understood as an
  adaptive system that changes its state based on a trained neural network based on historical data -
  time series of parameters of devices and their locations. The method is a two-level cycle of polling
  each element for grouping its neighbors and drawing up a network map. This network map shows
  the available connections, taking into account the current steam numbers of each device. The second
  (nested) polling cycle uses control information about the future state of the device and the
  connectivity of the group as a whole. Making changes to the network map instances by each device
  and updating the network map instances allows, upon completion of the polling cycles, to obtain
  the configuration of working devices. The results of the comparative analysis showed that management
  methods based on the principles of self-organization and adaptive change in structure are
  the most suitable for dynamic reconfiguration of the group. This result is possible due to the support
  of forecasting steps.

• A MATHEMATICAL MODEL AND PRODUCT MANAGEMENT SCHEME FOR IMPLEMENTING PARALLEL PRODUCT COMPUTING

  Е. А. Titenko , Т. М. Belova , I. I. Puzanov , А.А. Polozhenets , L. А. Lisitsin

  283-298

  2026-09-10

  Abstract ▼

  Relevance. Effective mathematical models for organizing parallel computing utilize principles of simultaneous rule execution on independent data fragments, as well as methods for processing symbolic information as a unifying category for various data types. Production systems in A.A. Markov Jr.'s notation offer the necessary potential for creating such models, but their standard control scheme is sequential, limiting their application in applied problems. Therefore, synthesizing modified production systems and their control schemes aimed at parallelizing the computational process of processing symbolic information is a pressing issue. The goal of this study is to reduce the execution time of a modified production model through bidirectional processing of symbol strings. The solution method is based on the application of principles of bidirectional grammatical parsing from the theory of syntactic analysis and compilation in algorithmic production systems and consists of modifying A.A. Markov's standard production computation scheme. This is achieved by introducing single-shot productions, bidirectional access to the string being processed, decomposing the original system into sections, and introducing a set of guard conditions for conflict resolution. The production model is implemented for typical symbolic processing tasks: word tagging and word reversal. Results. The structure of a modified production system was developed that overcomes the limitation of A.A. Markov's standard scheme—the sequential nature of computations. As a result of the study, a formal model of serial-parallel processing was created, a new control scheme was developed, and the correctness of the computations was demonstrated. Simulation on typical tasks showed a reduction in word processing time by almost half, achieved, in part, by eliminating the mandatory return to the first production in the control scheme and aggregating productions into sections. Conclusion. The study confirmed the feasibility and effectiveness of transforming A.A. Markov's sequential production systems into serial-parallel production models that produce correct results. A promising area of application is methods and software and hardware in homogeneous computing systems for high-performance processing of symbolic information

• UNITARY CODE CONVERTERS FOR HOMOGENEOUS COMPUTING SYSTEMS

  Е.А. Titenko

  104-115

  2025-11-10

  Abstract ▼

  Relevance. Effective operation of computing systems, among other things, is based on generally significant supporting calculations for planning parallel calculations and analyzing the results. Converters (formers) of unitary codes that combine the properties of numerical and symbolic information are quite important computing units. The purpose of the work is to create high-performance computing tools for processing unitary codes on a single theoretical basis. Research methods. Known one-dimensional and two-dimensional iterative networks are the basis for creating homogeneous converters of unitary codes that have the necessary and sufficient conditions for organizing parallel calculations. To synthesize unitary code converters, the following processing principles inherent in numbers and strings were identified: bidirectional processing, splitting into many local processes with their own starting points, hierarchy, multifunctionality, digit/symbol dualism. The described converters use known and introduce new circuit solutions. A digital compressor, a generator of a series of logical "1", an arbiter, a threshold element of weight and unitary codes are described. Results and discussions. Practically significant circuits of direct and inverse converters of "8-4-2-1 – normalized code" codes are created, used in homogeneous computing systems - multiprocessors, associative processors, etc. Quantitative assessments of unitary code converters are carried out for the created converter – a threshold element of weight and unitary codes. This converter is based on the dual interpretation of code elements as a digit and a symbol, which made it possible to exclude the linear time dependence on obtaining the result of comparing two codes at the final stage of calculations (versus the standard method). It is shown that for unitary codes of sizes from 12 to 36 bits, the time gain is 14-16%. This effect is obtained by eliminating sequential calculations between the cells of the iterative network. Conclusions. To construct effective time-saving schemes for converting unitary codes, the apparatus of iterative networks was used and developed, on the basis of which one-dimensional and two-dimensional iterative networks with regular connections were created, as well as converters based on universal logical modules

• HARDWARE AND SOFTWARE MEANS FOR DYNAMIC RECONFIGURATION OF A GROUP OF SMALL SPACE VEHICLES

  S.N. Emelyanov, S.N. Frolov, Е.А. Titenko, D.P. Teterin, А.P. Loktionov

  2024-08-12

  Abstract ▼

  The goal of the study is to automate the control of a group of nanosatellites in conditions of its
  variable number by updating its state based on sending and processing broadcast requests between
  nanosatellites and using the Transformer neural network. A neural network is needed to make predi ctions
  about the state of the spacecraft network. The problem of ensuring connectivity of a network of
  nanosatellites is studied, which comes down to the implementation of adaptive network control with
  assessment and prediction of the state of communication channels between pairs of devices based on a
  neural network. Dynamic reconfiguration and machine learning of a network of devices have been developed.
  Algorithmic tools have been defined for the initial training of a neural network and its subs equent
  additional training, taking into account the preprocessing of the original sparse or fully connected
  data sets about the network of devices. Upon completion of training on synthetic data, the created
  neural network is able to predict the quality of communication, taking into account line of sight, signal
  attenuation depending on distance and the state of the nanosatellite hardware platform. The developed
  software system performs deterministic reconfiguration based on the current state of the nanosatellite
  network and adaptive reconfiguration based on historical data by analyzing the hidden patterns of
  nanosatellite functioning using the Transformer neural network. To predict the quality of communication,
  a functional is used to connect the geodetic coordinates of pairs of satellites and the vectors of
  their states with the elements of the matrix of the quality of communication between nanosatellites with
  a given initial time, the value of the time interval, and the value of the sampling step of the measurement
  process. The use of neural networks implemented on GPUs made it possible to predict possible
  states of nanosatellites and carry out reconfiguration of the constellation ahead of schedule, including
  removing “problematic” nanosatellites from the network.

• NEURAL NETWORK ARCHITECTURE BASED ON GRAPH CODES

  V.S. Usatyuk, S.I. Egorov, А.P. Loktionov, Е. А. Titenko, I.Е. Chernetskaya

  2023-12-11

  Abstract ▼

  One of the important achievements of the theory of error-correcting coding is the discovery
  of graph codes and their important subset - low-density parity check codes (LDPC codes). Using
  the parity check matrix of the code on the graph, one can obtain a Markov random field. LDPC
  code can be embedded in an Ising model (a type of Markov random field) by using a torus topology
  with negative curvature. In this case, codewords correspond to saddle points (extrema) in the
  model, and trappin sets correspond to local minima. The use of LDPC codes with an increased
  code distance allows for maximum separation of saddle points, and thus increases the noise resistance
  of the neural network and the representation power. At the same time, the block and
  sparse structure, characteristic of a torus of negative curvature, simplifies multiplexing and reduces
  the number of trainable parameters of the neural network. The aim of the research is to
  reduce the computational complexity and increase the accuracy of neural networks through the
  use of a priori structural (quasi-cyclic) sparse graphs for a wide class of machine learning problems
  on Markov random fields. The paper presents a new approach that allows the synthesis of
  neural network architectures based on graph codes. The proposed approach provides an effective
  representation of Markov random fields through the use of QC-LDPC matrices and tensors.
  The proposed approach allows us to reduce the number of trainable parameters and logarithmically
  reduce the complexity of tensor multiplexing. The proposed approach provided an accuracy
  of 94.95% (1.72% to first place) of the binary classification problem “Pathfinder” of the “Long
  Range Arena” competition, with more than 5 times fewer parameters (multiplications). Application
  of the proposed approach to factorization problems on dense graphs, network problems, surface
  meshes, covariance matrices made it possible to increase the accuracy of reconstruction using
  the Frobenius metric in individual problems by more than 8 orders of magnitude in combination
  with simplifying the structure of the multiplexer.

• RECONFIGURATION METAGRAMMATICS FOR DESCRIPTION AND MODELING OF MULTI-STAGE COMPLEX ATTACKS

  О.I. Atakishchev, V.G. Gribunin, V.E. Ananyev, Е.А. Titenko

  2023-02-17

  Abstract ▼

  The purpose of the study is determined by a significant expansion of the classes of threats to
  modern automated systems, the dynamic development of tactics and techniques for attacking their
  information resources. The available methods and hardware and software tools effectively resist
  single-stage attacks that have a fixed scheme of destructive impact and time-limited activity. Modern
  types of destructive influences are understood as multi-stage complex attacks, for which it is
  important to create an adequate and effective apparatus for describing, modeling and repelling
  new types of attacks. Research methods are based on the development of a structural-algebraic
  approach, primarily on the apparatus of formal grammars and metagrammars. It has been established
  that the well-known formal models for describing and modeling multi-stage complex attacks
  are cumbersome, and their modification is difficult. Most attack descriptors are not equipped with
  a representative set of methods for structural and algebraic analysis of such complexly structured
  objects. To describe, model and repel such attacks, a class of reconfiguration metagrammars has
  been developed. These metagrammars contain a set of regular and reconfiguration rules for
  matching between grammar elements within the grammar. These rules allow you to select specific
  branches of the search graph depending on the achieved parsing states. This property significantly
  reduces the search space and thus increases the specific efficiency of the search. The developed
  apparatus of reconfiguration metagrammars creates the necessary theoretical basis for their effective
  use in modeling and reflecting existing and prospective ICAs that have a structural-linguistic
  description. The resulting qualimetric five-dimensional diagram, built on a set of practically significant
  indicators (homogeneity, connectivity, compactness, adaptability, directionality) showed
  the advantage of reconfiguration metagrammars over general metagrammars. Methods of parsing
  in reconfiguration metagrammars differ in structural rules of reconfiguration (structural adaptation)
  and selection criteria for their adaptation. These procedural features make it possible to
  expand the possibilities of attack modeling and improve the efficiency of procedures for repelling
  multi-stage complex attacks.

• A METHOD ENCODING TRANSMITTED MESSAGES IN THE ADS-B SYSTEM USING A CELLULAR AUTOMATIC

  D.M. Zarubin, V.P. Dobritsa, Е.A. Titenko

  2023-02-17

  Abstract ▼

  The purpose of the study is to develop a method for encoding of transmitted ADS-B messages
  between aircraft. The open format 1090ES of transmitted data is critical in terms of carrying
  out various types of attacks that can lead to a violation of the safety of aircraft operations.
  The work is aimed at using means of encoding and decoding messages with a private key. Research
  methods are based on the application and development of streaming data encryption using
  one-dimensional cellular automata. They operate as a generator of pseudo-random sequences that
  transform the elementary states of a cell of a one-dimensional cellular automaton based on typical
  hardware-oriented operations. The processes of encoding and decoding data fields are based on
  an analytical expression using typical logical operations (or, xor). This property allows parallel
  processing of message data fields. The result is the created method for ensuring the protection of
  transmitted data, additionally encoding on transmission and decoding on message reception.
  A distinctive feature of the method is the preservation of the protocol forma. The method uses a
  one-dimensional cellular automaton that encodes and decodes the target fields (coordinates, heading,
  etc.) using a pseudo-random number generator. The developed method belongs to the class of
  hardware-oriented methods. Critical for encoding and decoding properties of periodicity of data
  fields and key length are eliminated by choosing an initial irrational value and organizing the
  “streaming” work of the encoder. If the encoding automaton is running in streaming mode, the
  current value depends on the history of some depth, determining the length of the "automatic key"
  from the ADS-B message will be algorithmically impossible due to data loss. The linear complexity
  of the method allows you to perform transformations at the data rate. Conclusion: the development
  of hardware-oriented methods of data encoding makes it possible to increase the efficiency of
  using the ADS-B system by counteracting various types of destructive actions.

• SWITCHING MODEL OF PARALLEL COMPARISONS FOR A DATA FLOW RULE BASED SYSTEMS

  E.A. Titenko, E.V. Taldykin

  2021-02-25

  Abstract ▼

  The article is show the reduction of time spent on generating combinations of elements of
  the set. The elements of the set are formed from samples (left parts) of the production rules. The
  main task is to build time-efficient schemes (algorithms) for parallel generation of combinations of
  array elements. With regard to production systems, such schemes are necessary for the activation
  of a subset of products applicable to character data in the current step. The basis is taken and
  developed the well-known algorithm of the parallel bubble. The switching circuit "parallel bubble"
  consists of two alternating variants of switching elements in pairs. These commutations are based
  on local union into pairs of array elements with adjacent indices. Such a local combination of
  elements into pairs leads to "small" displacements of elements along the length of the array and
  the regular nature of the generation of pairs. In each pair, the operation of comparison-exchange
  of operands is performed. For production systems, the comparison operation is reduced to the
  search for sample intersections and the formation of a list of conflicting words. The reduction in
  the generation time of combinations is based on the construction of switching options with distributed
  combining of elements in pairs with a step equal to 4. The developed switching scheme contains
  on odd switching steps with a local combination of elements in pairs. In even-numbered
  steps, a switching accelerator is performed with a distributed combination of elements in pairs.
  The simulation of the work of the developed switching scheme was carried out on typical tasks of
  sorting and complete enumeration of pairs of elements. The reduction of time costs compared with
  the scheme "parallel bubble" by 15-18%. A linear dependence of the sorting time with a slope
  angle less than 1 was determined. This allows the use of a switching circuit for large-scale production
  systems. Local and distributed communications in the switching scheme preserve the
  property of regularity. This feature determines the hardware implementation of the circuit in the
  form of a parallel switch with natural scaling. This scheme can be used in a specialized production
  device for decomposing a production system into independent subsets of products.