TOLERANCE SYNTHESIS BASED ON SENSITIVITY ANALYSIS
Keywords:
Discrete passive elements, tolerances, production yield, operability margin, computer-aided design, measurement instrument, sensitivity analysis, worst case method, statistical method, spreadsheetAbstract
The tolerance allocation for passive discrete elements of analog devices is an important task
when planning mass serial production. Permissible deviations from rated values affects on the cost, the
choice of preferred number series for parameters and the acquisition availability of these components.
The element tolerances, as well as the temperature dependence and aging effects, are the key factors
affecting the product performances and the yield. The solution of this problem has received attention in
the scientific and technical literature for more than 40 years. During this time, the tools for designing
electronic devices have changed. Computer-aided design (CAD) systems for electronics - Electronic
Design Automation (EDA) have become widely used, providing an end-to-end design flow. Modern
EDAs have limited capabilities for tolerance design, providing a solution to the problem of tolerance
analysis. EDA users have to determine element tolerances based on their intuition and experience
through time-consuming interactive optimization. Using specialized tolerance software tools without
integration with professional grade EDA is not an acceptable solution. The purpose of the study is to
substantiate decisions for the tolerance synthesis in the end-to-end design flow in the EDA environment.
The article discusses methods for determining tolerances using the results of sensitivity analysis. Sensitivities
can be obtained using standard EDA tools. The implementation of these methods in the Excel
environment is considered. To exchange data between the spreadsheet and the EDA schematic databases
is proposed to use the clipboard. The proposed solutions make it possible to reduce the number of
interactive operations and time spent when tolerance allocation. An example of analog device tolerance
design in the EDA environment is given.








