METHODOLOGY OF TOPOLOGICAL RESTRICTIONS FOR INTENSIVELY USED FPGA RESOURCE

Abstract

In the paper we consider the problem of achieving high real performance of reconfigurable computer systems in implementing computationally expensive tasks from various problem areas. The parameters of the programs executed on reconfigurable systems determine their real performance. The main component of these programs is the computing data processing structures implemented as FPGA configuration files. At the same time, one of the key parameters of any computing structure is the clock frequency of its operation, which directly affects its performance. However, there are several problems concerning the achievement of high clock rates, and they cannot be solved with the help of modern CAD tools. The reason is the non-optimal topological placement of functional blocks of the computing structure within the field of FPGA primitives, especially with high resource utilization. Due to this, the load on the FPGA switching matrix is increasing, and, as a result, the connections among functionally dependent FPGA primitives turn out to be much longer than is acceptable. In addition, excessive connection length is observed when tracing connections among primitives that are placed on different FPGA chips or are physically separated by on-chip peripherals. In the paper we describe a methodology which provides optimization of the placement of computing structure elements on FPGA primitives, and minimizes the length of traces among primitives, and also minimizes the number of traces among physically separated FPGA topological sections. To prove the proposed methodology, we implemented the test task "FIR-filter" on a reconfigurable computer "Tertius." We have demonstrated the main problems concerning reaching the target clock rate and have described a method for their solution. Owing to our methodology, it is possible to increase the clock rate; hence, the performance of Tertius will increase by 25% without revising the functional circuit of the task’s computing structure. According to our current research of the suggested methodology and its efficiency, we claim that CAD tools, used for creating topological restrictions and based on our methodology, will significantly reduce the time for developing programs with the required characteristics for reconfigurable computer systems.