CIRCUIT DESIGN METHOD FOR IMPROVING LARGE-SIGNAL SPEED OF CLASSICAL OUTPUT STAGES OF OPERATIONAL AMPLIFIERS USING BJT (CMOS, JFET OR SIGE) TRANSISTORS
Abstract
A significant drawback of classical output stages of microelectronic operational amplifiers, which today are implemented based on BJTs (bipolar junction transistors), CMOS (complementary metal-oxide-semiconductor transistors), or JFETs (junction field-effect transistors), including when these technologies are used together, is that they exhibit a relatively low output voltage slew rate under the influence of large-amplitude pulsed input signals. This undesirable effect is mainly caused by the presence of parasitic capacitances inherent in the reference current source circuits employed and in their output transistors. This paper discusses an original and effective circuit design technique that provides forced recharging of parasitic capacitances, which is used in output stages implemented in numerous patents of the world’s leading microelectronic companies. The introduction of a special differentiating transient correction circuit into the original schematics, as well as various options for its practical implementation, are considered for the first time. The circuitry of such output stages is protected by a patent of the Russian Federation. Four different modifications of buffer amplifiers have been developed and investigated, which are intended for use in modern technological processes implemented with silicon BJT or CMOS transistors, as well as with gallium arsenide n-JFET and p-n-p bipolar transistors. Examples of computer simulation of DC operating modes, as well as transient processes, are presented, which clearly demonstrate a significant increase in the maximum output voltage slew rate (by more than one to three orders of magnitude). The proposed advanced circuit solutions for GaAs transistors are recommended for practical application in microelectronic devices designed for operation under elevated temperature conditions.
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