CIRCUITRY METHODS FOR INCREASING THE SPEED OF OPERATIONAL AMPLIFIERS BASED ON A "FOLDED" CASCODE

Abstract

Three circuit techniques are proposed that provide (with simultaneous use) an increase by more than two orders of magnitude of the maximum output voltage slew rate (SR) of microelectronic operational amplifiers (op-amps) based on bipolar transistors with a classical architecture, designed to operate in automatic control systems, radio engineering and communications, for example, as drivers for ultra-high-speed analog-to-digital converters (EVIOAS150, EVIOAS350, AD9208, AD9691, 1273PV14, etc.). The considered op-amps contain a cascode input stage with a non-linear correction of the pass-through characteristic and a tracking circuit that increases the attenuation coefficient of the input common-mode signals and the noise suppression coefficient on the power buses, as well as an intermediate stage based on a “folded” cascode. The use of a "folded" cascode makes it possible to increase the efficiency of using power supply voltages, as well as to increase the unity gain frequency of the corrected op-amp. However, such an intermediate stage is an essential non-linear link that limits the maximum output currents that recharge the op-amp correction capacitor. The results of computer simulation of two modifications of the AmpSR1, AmpSR2 op amps, which differ from each other in the structure of a nonlinear parallel channel, which eliminates the dynamic overload of a "folded" cascode, are presented. The relevance of the research performed is related to the problems of import substitution in the class of high-speed op-amps and the lack of new and promising ideas for increasing the SR of the op-amp based on the simultaneous use of non-linear and differentiating transient correction circuits in the large signal mode among analog circuit designers. The considered circuit techniques are also effective when using CMOS technological processes.