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Article title PHYSICAL MODEL OF REGULAR STRUCTURES BASED ON FINFET TRANSISTORS WITH INDEPENDENT GATES
Authors S. V. Gavrilov, E. S. Kareva, D. I. Ryzhova, A. N. Schelokov
Section SECTION IV. COMPUTER SCIENCE AND ELECTRONICS
Month, Year 07, 2017 @en
Index UDC 621.3.049.771.14
DOI
Abstract With the increase in the degree of integration and the decrease in the technological dimen-sions of transistors, a new research field in nanoelectronics has been formed – the design of CMOS circuit based on the FinFETs (Fin Field Effect Transistors). By using the three-dimensional gate of the FinFET in the form of a fin, the effective gate width increases at the same area of the logic cell. With each transition to new technological processes, the influence of design rules increases. A homogeneous layout reduces the resulting area and the number of constraints and rules which must be observed in design. In this regard, we use regular structures in the layout design. In this paper, we consider methods of layout development based on the regular FinFET template and based on the technology of cutting layers. As a result, we developed topological models of logical elements for both methods. For the method of regular layout design with cutting layers, a formula relation for determining the number of different layout variants is derived. We proposed a method of searching for the most compact layout designs and presented compact layout of circuits for IG FinFETs logical elements. The proposed method provides more efficient use of polysilicon for the realization of gate IG FinFETs. Unlike similar methods, it allows reducing the area of the final layout by a factor of 1.5 (by reducing the number of isolating gates).

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Keywords Fin Field Effect Transistor (FinFET); logical synthesis; physical synthesis; serial-parallel directed acyclic graph (SP-DAG); regular structure; transistor pattern.
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